FIG. 1 shows a prior art semiconductor circuit 10 in which a p-channel thin film transistor is formed over an underlying n-channel metal oxide semiconductor field effect transistor (MOSFET). The transistors are connected to form a CMOS inverter.
The underlying MOSFET comprises heavily doped n-type (n+) underlying transistor active regions 12 and 14 formed in a lightly doped p-type (p-) silicon or other semiconductor substrate 16, a channel region 18 in substrate 16 between underlying n+ active regions 12 and 14, and a conductively doped polysilicon gate 20 over channel region 18. Gate 20 has a top surface 22 and sidewalls 24. An underlying gate oxide layer 26 insulates gate 20 and channel region 18 from each other.
Gate 20 functions as a gate for both the MOSFET and the thin film transistor. Spacers 38 are formed along gate sidewalls 24 to a thickness of which is generally over 1000 Angstroms. Spacers 38 are used to create lightly doped regions within underlying MOSFET active regions 12 and 14 beneath spacers 38. The lightly doped regions are created by performing a light implanting or active regions 12 and 14 before spacers 38 are formed on sidewalls 24. A heavier implanting of active regions 12 and 14 is performed after spacers 38 are formed, with spacers 38 blocking or restricting the heavier implanting thereunder.
The thin film transistor comprises gate 20, heavily doped p-type (p+) thin film active regions 30 and 32, and a thin film channel region 34 between thin film active regions 30 and 32. Thin film channel region 34 is slightly offset from transistor gate top surface 22, extending somewhat beyond transistor gate top surface 22. Such an offset reduces leakage current in thin film transistors. Channel region 34 is formed of lightly doped n-type (n-) silicon.
An isolation oxide layer 36 insulates gate 20 and underlying active regions 12 and 14 from thin film active regions 30 and 32 and from thin film channel region 34. Isolation oxide layer 36 typically has a thickness of greater than about 2000 Angstroms over underlying active regions 12 and 14 to isolate the MOSFET from the thin film transistor. Isolation oxide layer 36 is thinner over transistor gate top surface 22 so that gate 20 will gate thin film channel region 34. Isolation oxide layer 36 has a typical thickness over top surface 22 of about 100 Angstroms to about 800 Angstroms.
Underlying active region 12 forms the source of the underlying n-channel MOSFET and is typically connected to V.sub.ss or ground. Thin film transistor active region 30 forms the source of the underlying p-channel thin film transistor and is typically connected to V.sub.cc or a positive logic voltage. Underlying active region 14 forms the drain of the MOSFET and thin film active region 32 forms the drain of the thin film transistor. The two drains are connected to a common n+ conductive runner 40. Semiconductor circuit 10 thus forms a CMOS inverter. Gate 20 forms the input of the inverter and conductive runner 40 forms the output.
A problem arises in prior art thin film transistors such as described above when the junction between thin film source 30 and thin film channel region 34 is not accurately aligned with gate 20. FIGS. 2 and 3 show examples of inaccurate gate alignment.
In FIG. 2, the junction between thin film source 30 and thin film channel region 34 is located too far in the direction of thin film drain region 32. This alignment results in an offset region, indicated by the reference numeral 50, which is significantly longer than the corresponding optimal offset region of FIG. 1. The longer offset region decreases the transistor's conductivity when turned on.
In FIG. 3, the junction between thin film source 30 and thin film channel region 34 is located too far in the direction of thin film source region 30. A portion of channel region 34, indicated by the reference numeral 52, overlies spacer 38 and is not gated at all. In addition, there is no offset region since the junction between thin film drain region 32 and thin film channel region 34 is directly over gate 20. Without an offset region, the transistor shown in FIG. 3 has a significantly larger leakage current than the transistor shown in FIG. 1.
The invention described below overcomes the misalignment problems mentioned above, while creating a greater effective thin film transistor gate length and a self-aligned thin film transistor source. According to the methods described below, only two layers of polysilicon are required to create a CMOS inverter which utilizes a thin film transistor over an underlying MOSFET.